In many modern high density integrated circuits many different but related functions occur in response to a clock signal which is external to the integrated circuit. One example is dynamic random access memories (DRAMs) in which there are many internal functions, such as precharging various nodes and enabling various circuits, in response to an external signal. In the case of a typical DRAM there are two external clock signals used during normal operation. The various internal functions, which have a timing relation to each other, are performed in response to internal clock signals generated in response to one of the external clock signals. These internal clock signals are timed in relation to each. This timing relation is achieved by sequentially enabling clock generators. For example a first clock signal is generated by a clock generator in response to an external clock signal. The first clock signal is received by a second clock generator which in turn generates a second internal clock signal. Likewise a third internal signal is generated by a third clock generator in response to the second clock signal. Likewise other internal clock signals are generated in this sequential manner. The various functions to be performed are typically required to be performed in a predetermined sequence for the integrated circuit to function. With sequentially generated internal clock signals, the order in which these internal clock signals occurs is certain. Consequently, the sequence of the internal functions can be controlled by using these sequentially generated internal clock signals.
The problem with this technique, however, is identifying the location of a failure. If one internal clock fails to occur, then all of the subsequent ones will also fail to occur. Because it is very difficult to trace a signal on a high density integrated circuit, an internal clock failure is difficult to locate. This can be a problem in testing a design or in identifying failure modes during production. Memory cell failures are relatively easily identified when the part is functional. When an internal clock fails, however, the integrated circuit will have the appearance of not functioning at all. Consequently, the location of the cause of the failure can be extremely difficult to locate. In the design stage, the ability to locate such a failure mode is critical in correcting the design to obtain a functional design. In production the ability to identify failure modes can lead to a corrective design to enhance yields.